This invention relates to an abnormal voltage detection circuit which can be incorporated into a large scale integrated circuit (LSI) for an electronic clock, for example.
Recently, there have been developed a variety of electronic clocks with batteries and the like used as a driving source. If the supply voltage is extremely lowered by any shock or the like applied to these kinds of electronic clocks, for example, then the LSI for clock use will cease to operate properly, thereby providing an incorrect indication of time. Therefore, it is needed to incorporate into the clock LSI an abnormal voltage detection circuit for monitoring the supply voltage level.
FIG. 1 shows a conventional abnormal voltage detection circuit, and FIG. 2 is a waveform diagram of voltages at several circuit points of the abnormal voltage detection circuit of FIG. 1. The abnormal voltage detection circuit of FIG. 1 is driven by a negative power source V.sub.DD composed of an AC power source and a rectifier circuit. Across the negative power source V.sub.DD is coupled by means of a switch SW1 a series circuit of a depression-type (D-type) P-channel metal insulated semiconductor field effect transistor (MIS FET) Q1 and an enchancement-type (E-type) P-channel MIS FET Q2. The gate and source of the FET Q1 are coupled to each other, while the gate of the FET Q2 is coupled to the negative power source V.sub.DD. Further, a series circuit of a D-type P-channel MIS FET Q3 and an E-type P-channel MIS FET Q4 is coupled across the negative power source V.sub.DD. The gate and source of the FET Q3 are coupled to each other, while the gate of the FET Q4 is coupled to the junction of the FET's Q1 and Q2. A capacitor C1 is a stray capacitor formed between the gate and source of the FET Q4.
In the abnormal voltage detection circuit as shown in FIG. 1, the FET's Q1 and Q4 are so formed as to have a lower mutual conductance as compared with the FET's Q2 and Q3, the threshold voltage of the FET Q2 is set a little lower than V.sub.DD, and the threshold voltage of the FET Q4 is set lower than that of the FET Q2.
In this abnormal voltage detection circuit, when the switch SW1 is closed, that is, when the power supply, having been once cut off due to power failure or the like, is resumed, the voltage applied to the gate of the FET Q2 substantially rectilinearly rises up to the supply voltage V.sub.DD, as indicated by curve V.sub.G2 of FIG. 2. Also, the gate voltage of the FET Q4 rectilinearly rises accompanying curve V.sub.G2, as indicated by curve V.sub.G4. Before the gate voltage V.sub.G4 of the FET Q4 reaaches the threshold voltage V.sub.TH4 thereof, the FET Q4 is nonconducting, and the output voltage V.sub.OUT of the abnormal voltage detection circuit rises along curve V.sub.G2. When the gate voltage V.sub.G4 of the FET Q4 is made equal to the threshold voltage V.sub.TH4, the FET Q4 conducts, and the output voltage V.sub.OUT of the circuit drops to the earth potential. Thereafter, when the gate voltage V.sub.G2 of the FET Q2 reaches the threshold voltage V.sub.TH2 thereof, the FET Q2 is caused to conduct, lowering the gate voltage V.sub.G4 of the FET Q4 down to the earth potential. Consequently, the FET Q4 is rendered nonconducting, and the circuit output voltage V.sub.OUT rises up to the level of the supply voltage. If the output voltage of the negative power source V.sub.DD is not high enough to allow the gate voltage V.sub.G2 of the FET Q2 to reach the threshold voltage V.sub.TH2, then the FET Q2 is prohibited from conducting, so that the FET Q4 is kept conductive and the output voltage V.sub.OUT is kept at a low level to energize the display unit 1, and thus an abnormal voltage is detected.
Thus, the abnormal voltage detection circuit as shown in FIG. 1 may satisfactorily operate with the power source V.sub.DD to produce DC voltages by rectifying AC. However, with a DC power source such as batteries, it may not properly operate for the following reason. That is, when the switch SW1 is closed, the gate voltage V.sub.GD2 of the FET Q2 rapidly rises in such a manner as indicated by a broken line in FIG. 2. In this case the gate voltage of the FET Q4 rises slowly, because it is obtained as the output voltage of an integration circuit formed of the FET Q1 and the stray capacitor C1. Accordingly, the FET Q2 is caused to conduct before the FET Q4 is allowed to conduct, thus permanently prohibiting the FET Q4 from conducting. As a result, the abnormal voltage detection circuit produces the voltage V.sub.DD, which prevents detection of abnormal voltages.